Synopsys Off Campus Hiring Freshers For Digital Design Engineer Position- BE/BTech/ME/MTech

Synopsys Off Campus Hiring Details:

About Synopsys: At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

Job Profile: ASIC Digital Design Engineer

Company Name: Synopsys Inc

Company Location: Mumbai, Maharashtra, India

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Experience Required: Freshers

Job Description and Requirements for Synopsys Off Campus Hiring

ASIC Digital Design Engineer
We’re looking for ASIC Digital Design Engineer to join our team.

Seeking a highly motivated and innovative mixed signal co-simulation verification engineer manager with strong theoretical and practical background in high-speed data recovery circuits. Needs to have good people management skills. Working as part of a highly experienced mixed-signal design team, the candidate will be involved in managing team (with some hands on work) in  verifying current and next generation Backplane Ethernet, PCIe, SATA, and USB 2/3 SERDES products. The position offers an excellent opportunity to work with an expert team of digital, analog and mixed signal engineers responsible for delivering high-end mixed-signal designs.

Remote work is optional for this position.

Key Qualifications required for Synopsys Off Campus Hiring
  • Enrolled in Electrical Engineering program and have basic knowledge about analog circuitry designs such as bandgap, opamp, PLL
  • Experience writing scripts in languages such as Perl, Python  and Unix shell.  The ideal candidate would be familiar with Verilog and System Verilog
Preferred Experience for Synopsys Off Campus Hiring
  • Managing team, making project plans, tracking it, addressing dependencies, status reporting
  • modifying/using the existing UVM and VMM  System Verilog test benches to co-simulate mixed signal designs
  • analyzing/verifying the functionalities of SERDES
  • Defining and tracking verification test plans
  • Debugging simulation failures in both analog and digital domains
  • Creating top level analog test benches for SERDES
  • Performing physic layout reliability analysis for SERDES.

Apply Before the link Expires for Synopsys Off Campus Hiring.

Apply Link- Click here to Apply for Synopsys Off Campus Hiring

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