About the Company: Communication & Devices Group: The wireless revolution at Intel! We are one team – passionate engineers and technologists from diverse industry backgrounds working together to realize a world of connected computing. We are bringing the best ideas from the brightest minds to deliver future mobile experiences into the market. We are on the journey towards making Intel a wireless leader with exciting products for the Internet of Things, 5G and an opportunity to change the world with your work.
Job Profile: Under Graduate Intern – Technical
Degree Needed: M.E/M.Tech/MS
Exp Needed: Freshers
Work Location: Bangalore
- In this position, you will be involving in the training, design and development of next generation Server SOCs/CPUs.
- Your responsibilities will include some of the following but not limited to: – Assist design unit owner in Register Transfer Level RTL modeling & functional validation.
- Use EDA tools extensively to simulate logic behavior and circuit performance and direction of physical design for next generation, deep sub-micron embedded circuit solutions.
- Verify the circuit behavior against the original simulation model and first silicon. – Define VLSI Structural Design methodology and developing design flows. Implement structural physical designs, such as synthesis, floor planning, power-grid and clock tree designs, timing budgeting and closure, place and route, RC-extraction and integration.
- Verify structural physical designs, such as functional equivalency, timing/performance, noise, layout design rules, reliability and power.
- Develop Analog IP on next generation deep submicron process for the Intel’s SOC, perform tasks related to Very-large-scale integration VLSI complementary metal-oxide-semiconductor CMOS IC design, Solid state physics and physical layout. Such tasks may include: Circuit design of high speed clocking related circuits [phase-locked loop PLL, delay-locked loop DLL, bandgap] or high voltage input/output IO [double data rate DDR/LPDDR, General-purpose input/output GPIO, OPIO].
- Responsible for Integration of Third party IPs — Synthesis, functional and/or timing convergence, and pre and post-si debug of IPs developed by various external vendors as well as within the company. Handling of signals crossing power planes and clock domains, industry standard protocols including hardware and software details dealing with Memory LPDDR, storage eMMC, SATA, UFS, peripherals PCIe, USB, and MIPI interfaces in SOC devices. System integration dealing with Si/ Platform/ FW/ MW/ drivers/ OS/ Apps on Android & Windows-based tablets and phones.
- You should be a student Post graduate/Masters – ME/MTech/MS currently pursuing studies in relevant field with good understanding of semiconductor physics and basic PC computer architecture.
- Additional qualifications include: – Familiarity with Very Large Scale Integration VLSI Complementary Metal-Oxide Semiconductor CMOS logic circuit design – Well versed in UNIX*, C programming and relevant Computer Aided Design CAD tools
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